Detailed Study on a Robust and Efficient Fault-Resilient Rad Hard ADPLL

Typical analogue modelling approaches are used in classical PLLs. However, integrating PLL with a noisy application environment is time-consuming and limited. According to current knowledge, the overwhelming majority of PLLs use Analog Loop Filters (ALFs) and Voltage Regulated Oscillators, all of which are notoriously difficult to implement in noisy environments. Traditional PLLs are unable to be ported to advanced processors. The advent of deep-submicron CMOS technologies in recent years has allowed the digitization of major conventional analogue circuits, including analogue PLLs, which could be crucial in overcoming the issues described above and achieving a more efficient solution than traditional analogue implementation. A FDLC-based architecture is used in the proposed ADPLL model. In terms of computational time, power consumption, and cost, this architecture model outperforms the conventional FD-ADPLL model.

Author (s) Details

Varsha Prasad
Department of ECE, RV Institute of Technology and Management, Bangalore, India.

Dr. S. Sandya
Department of ECE, RV Institute of Technology and Management, Bangalore, India.

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