Frequency Multiplier with Delay Locked Loop -Based Clock Generator for System on Chip Applications

Any implementation of a particular type of the multiplier in automatic frequency measurement systems is primarily determined by the total allowed variance of both the output frequency and the transducer’s input frequency. As a result, in transducers with such a small variance, it is normally better to use frequency multipliers from the first group. The suggested edge combines optimum pace and consistency with an organisational structure and an undetermined overlap. The proposed hybrid digital edge solution offers broadband with low-energy and low-area advantages, as well as being a candidate for low-energy frequency summaries in deep CMOS sub-micrometer. To incorporate the automatic interface, a counter was used instead of a charge pump. Both of the tools for operating stable clock pulses for device on chip applications, as well as the frequency multiplier, are part of the overall system. The frequency multiplication method is carried out with the aid of a clock amplification device based on an edge combiner and C2MOS logic. Finally, a computational analysis is performed to ensure that the output is correct. In comparison to other designs, it is clear that this device consumes less power in the same process.

Author (s) Details

G. Prasanna Kumar
ECE Department, Malla Reddy Engineering College (A), Hyderabad, Telangana, India.

J. Prabhakar
ECE Department, Nalla Malla Reddy Engineering College, Hyderabad, India.

Nagulancha Raju
ECE Department, Vignan Institute of Technology and Science, Hyderabad, Telangana, India.

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