This study proposes a 5V, 124mw 64-bit Advanced Comparator for DSP Processors. This research compares modified and current 64-bit binary comparator designs to show how they can reduce power consumption and latency. To increase the circuit’s performance, some changes were made to the current 64-bit binary comparator architecture. Simulation in Tanner EDA Tool is used to calculate the comparison of updated and existing 64-bit binary comparator designs.
Department of Electronics and Communication Engineering, Vaagdevi College of Engineering, Warangal, 506005, India.
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