A 5V 124MW 64 – Bit Advanced Comparator for DSP Processor

This study proposes a 5V, 124mw 64-bit Advanced Comparator for DSP Processors. This research compares modified and current 64-bit binary comparator designs to show how they can reduce power consumption and latency. To increase the circuit’s performance, some changes were made to the current 64-bit binary comparator architecture. Simulation in Tanner EDA Tool is used to calculate the comparison of updated and existing 64-bit binary comparator designs.

Author(s) Details

Thota Mounika
Department of Electronics and Communication Engineering, Vaagdevi College of Engineering, Warangal, 506005, India.

View Book :- https://stm.bookpi.org/AAER-V5/article/view/988

Leave a Reply

Your email address will not be published. Required fields are marked *